1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically to a semiconductor device with an output buffer circuit externally outputting data within the semiconductor device.
2. Description of the Background Art
With the recent increase in speed of semiconductor devices, increasingly higher drivability is required for output buffer circuits in semiconductor devices.
FIG. 11 is a first exemplary circuit diagram showing a basic arrangement of an output buffer circuit used in a conventional semiconductor memory device.
The output buffer circuit shown in FIG. 11 includes:
an output terminal DQr; a level shifter 206 receiving a first internal control signal HOUT generated in accordance with stored data to be output for shifting its H level from an internal down-converted potential Vcc down-converted from an external power supply potential Ext.Vcc to an internal boosted potential Vppo internally generated within the semiconductor device; an N channel MOS transistor 202 having its gate receiving an output from level shifter 206 and connected between external power supply potential Ext.Vcc and output terminal DQr; and an N channel MOS transistor 204 having its gate receiving a second internal control signal LOUT generated in accordance with stored data to be output and connected between output terminal DQr and a ground potential.
FIG. 12 is a diagram of operation waveforms shown in conjunction with the operation of the output buffer circuit in FIG. 11.
Referring to FIGS. 11 and 12, internal control signal HOUT rises to the H level at t1. At the time, assume that internal control signal LOUT, not shown in FIG. 12, is at an L level and N channel MOS transistor 204 is in a non-conductive state.
Operation of level shifter 206 allows a node N51, which is an output node of level shifter 206, to rise to the H level. Then, N channel MOS transistor 202 becomes conductive and the potential at output terminal DQr begins to rise.
Here, due to the state of a load connected to output terminal DQr outside the semiconductor device, ringing of the waveform may be caused for the signal to be output from output terminal DQr.
At t3, the potential of the signal to be output from output terminal DQr is stabilized.
The ringing may disadvantageously cause malfunction of other semiconductor devices or the like externally connected for receiving the output signal.
An improved output buffer circuit has been proposed in Japanese Patent Laying-Open No. 5-290582 as a circuit capable of reducing power supply noise during such output of signals. The output buffer circuit is used, for example, for driving a word line for the semiconductor memory device.
FIG. 13 is a circuit diagram showing an arrangement of a conventional output buffer circuit in the aforementioned laid open application.
Referring to FIG. 13, the output buffer circuit includes: an inverter 231 receiving and inverting an input signal S for outputting the inverted signal thereof to a node N131; an N channel MOS transistor 241 having its gate connected to node N131 and connecting a power supply potential Vcc and an output terminal OUT; a delay circuit 232 receiving and delaying the output signal from inverter 231; a bootstrap circuit 233 receiving an output from delay circuit 232; and an N channel MOS transistor 242 having its gate connected node N133 and connecting power supply potential Vcc and output terminal OUT.
The output buffer circuit further includes an inverter 243 receiving and inverting an input signal R, and an N channel MOS transistor 244 having its gate receiving an output from inverter 243 and connecting a ground potential Vss and output terminal OUT.
Delay circuit 232 includes series connected inverters 232a and 232b.
FIG. 14 is a circuit diagram showing an arrangement of bootstrap circuit 233 shown in FIG. 13.
Referring to FIG. 14, bootstrap circuit 233 includes an inverter 211 receiving an input signal at an input node N110, and an inverter 212 receiving and inverting an output from inverter 211.
Outputs from inverters 211 and 212 are applied to nodes N111 and N112, respectively.
Bootstrap circuit 233 further includes: an N channel MOS transistor 213 having its gate receiving a power supply potential Vcc and connecting nodes N111 and N113; an N channel MOS transistor 214 having its gate receiving the potential of node N113 and connecting nodes N110 and N133; and a capacitor 215 connected between nodes N112 and N113.
Referring to FIGS. 13 and 14, given that input signal R is at H level and N channel MOS transistor 244 is in the non-conductive state, when input signal S falls from H to L level, the potential of node N131 first rises from L to H level by inverter 231.
Responsively, N channel MOS transistor 241 becomes conductive, so that the potential at output terminal OUT begins to rise from L to H level.
Thereafter, input node N110 for bootstrap circuit 233 rises from L to H level after a period of time delayed by delay circuit 232. Responsively, bootstrap circuit 233 shifts the potential of node N133 higher than power supply potential Vcc. Then, N channel MOS transistor 242 becomes sufficiently conductive, so that power supply potential Vcc is transmitted to output terminal OUT.
As described above, by sequentially rendering two output transistors in the output buffer circuit conductive, H level is gradually supplied for the output terminal, so that a large amount of current cannot flow into the output terminal from the node receiving power supply potential Vcc at a time. Thus, reduction in power supply noise is achieved.
Furthermore, when an input pulse in an impulse form is introduced to input signal S, electric charge may pass from node N133 to node N110 for bootstrap circuit 233. Though N channel MOS transistor 241 allows output terminal OUT to maintain H level, N channel MOS transistor 242 cannot maintain the stabilized conductive state due to decrease in the potential of node N133.
As described above, for the output buffer shown in FIG. 11, when the output transistor is increased in size to achieve higher drivability for the output buffer circuit due to a demand in speed, current rapidly flows from the output buffer circuit in the semiconductor device to the external load connected to the output terminal, thereby causing ringing.
On the other hand, the circuit described with reference to FIGS. 13 and 14 applies a gate potential of the output transistor using the bootstrap circuit. The output terminal however cannot maintain the level of power supply potential Vcc as H level for a long period of time as bootstrap circuit generates a high potential only for a given period of time.
In the generally used semiconductor device, load for the output buffer externally outputting a signal from the semiconductor device depends on the type of the externally connected circuit board and element, so that a constant rising time is not obtained for the output signal.
In addition, a semiconductor device with high operation frequency may be used for the application with low operation frequency.
Thus, the circuit shown in FIG. 13 may not suitably be used as an output buffer for outputting a signal to the outside the semiconductor device.